About me

I am a Lead Engineer Power Electronics at Eaton Research Labs (ERL), located in Menomonee Falls, WI, USA. I obtained my Ph.D. and M.Sc. degrees from the Spellman High Voltage Power Electronics Laboratory (SHVPEL) at Stony Brook University in 2022 and 2024, respectively, under the guidance of Prof. Fang Luo. I obtained my B.Sc. degree in Electrical Engineering with Honours from the University of Engineering and Technology, Lahore in Lahore, Pakistan in 2018.

During my Ph.D., I worked as a research intern in Summer 2022 at GE Aerospace Research (then GE Research), focusing on Hybrid Electric Propulsion. Prior to pursuing Ph.D., I worked as a Site Engineer with the Pak Matiari - Lahore Transmission Company Private Limited/China Electric Power Equipment and Technology, State Grid Corporation of China (SGCC) on the ±660 kV HVDC transmission line project in Pakistan. Earlier in my career, I served as a Research Analyst with Power Technology Research, where I did market research for developing transformer cost models.

Research Interests

I am interested in modular, heterogeneous integrated architectures for Wide‑Bandgap (WBG) and Ultra‑Wide‑Bandgap (UWBG)‑based power converters as we advance toward “Power Electronics 3.0,” driven by the challenges of an aging electric grid, rising industrial power demand, the growth of AI/ML data centers, and the electrification of transportation.

Heterogeneous integration is fundamentally a multi‑physics problem that encompasses electrical, mechanical, thermal, and embedded‑system design aspects. I am interested in the electro‑thermal co‑design space, with a primary focus on converter topologies, layout and packaging optimization, and mitigation of exacerbated side effects from fast switching (high \(\text{d}v/\text{d}t\) and \(\text{d}i/\text{d}t\)) such as electromagnetic interference (EMI), partial discharge (PD), and high‑frequency interactions. My goal is to develop architectures that inherently exhibit low side effects while achieving high power density and efficiency.

I explore converter topologies that are economical, efficient, retrofit‑friendly with existing control architectures, and inherently minimize side‑effect generation. In the realm of side effects, my focus lies in high‑fidelity, reduced‑order modeling that accurately captures system behavior within targeted frequency ranges and on packaging architectures that minimize side‑effect interactions while meeting mechanical and thermal constraints.

See my research and publications.